Phase-looked loop is a vitally important device. Phase-looked loop is analog and mixed signal building block used always in subsystem, system-on-chip, system IC, memory, telecommunication, communication, navigation system, computer, computer peripherals, automotive, networks, digital systems, consumer electronics, industrial, instrumentation, and any other fields that require frequency synthesizing, clock recovery, synchronization, clock generation, and/or the system's clock distribution. Phase-looked loop is a very versatile building block suitable for a variety of frequency synthesis, clock recovery, clock generation, and synchronization applications.
Prior Art FIG. 1 shows two types of conventional phase-locked loops, which are a conventional third-order phase-locked loop 110 and a conventional fourth-order phase-locked loop 120. The conventional third-order phase-locked loop 110 typically consists of a phase-frequency detector (or phase detector), a charge-pump, a second-order low-pass filter, a voltage-controlled oscillator, and a frequency divider in a loop. In addition, the conventional fourth-order phase-locked loop 120 typically consists of a phase-frequency detector (or phase detector), a charge-pump, a third-order low-pass filter, a buffer amplifier (or a gain amplifier), a voltage-controlled oscillator, and a frequency divider in a loop. Assuming that the frequency divider is considered as unity, the phase detector is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or phase detector). Therefore, change in the low-pass filter's output voltage is used to drive the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.
In the conventional phase-locked loops 110 and 120 of Prior Art FIG. 1, lock-in time is usually defined as time that is required to attain lock from an initial loop condition. In addition, system latency is here defined as an amount of time that passes from the generation of an event (i.e., the moment power is on, the moment something is initiated) until its realization (i.e., execution, the moment an effect begins). System latency is introduced into hardware, firmware, operating system (i.e., system software), kernel, and application software. System latency used here is hardware-related. However, the conventional phase-locked loops 110 and 120 have suffered from slow locking, which has increased system startup time. However, PLL synthesizers for wireless applications must provide fast lock-in time. For example, lock-in times of these PLLs which are used in GSM (i.e., global system for mobile), CDMA (i.e., code-division multiple access), AMPS (i.e., advanced mobile phone service), and TDMA (i.e., time-division multiple access) must be quick-within millisecond or less. Furthermore, frequency synthesizers are critical to both receivers and transmitters in a cellular/PCS handset In its digital mode, a fast lock-in time of less than 2 ms is required to satisfy MAHO (i.e., mobile-assisted hand-off operation) requirements. In its analog mode, UHF (i.e., ultra high frequency) synthesizer requires a fast lock-in time requirement in channel-scan mode. Recently lock-in times of PLL synthesizers for GSM evolution GPRS (i.e., general packet radio service), HSCSD (i.e., high-speed circuit-switched data), and EDGE (i.e., enhanced data rates for GSM evolution) are required to be fast Lock-in times of PLL synthesizers for future generation mobile technology might be required to be much faster. Moreover, PLL synthesizer for RBDS (i.e., radio broadcast data system) usually locks in 500 microseconds.
In addition, time-to-market has demanded to build and simulate a complete system which incorporates realistic and accurate behavioral representation for all design components including PLL-based clock distribution before tape-out PLL is used to synchronize all communications within the system. However, if a PLL has a slow lock-in time performance, it will prohibit the PLL behavior from being incorporated into the complete and realistic system simulation. The PLL behavior without lock-in time degrades simulation accuracy and adds serious bottleneck to the complete and realistic system simulation. Therefore, a fast lock-in time performance is one of main factors to obtain quick and accurate environment for the entire systems and to quickly and accurately verify the analog, digital, firmware, and software components of any large systems because the simulation time of the entire system containing PLL(s) and/or PLL-based clock distribution is absolutely proportional to time required the phase-locked loop(s) to lock.
System users have demanded to save time booting up their low-end systems such as personal computers and single-user workstations. The speed of system bootup time partially depends on how to use windows system. Moreover, the speed of system bootup time has also been degraded by the hardware system including conventional PLLs. Thus, fast lock-in time performance definitely enables any system to start up fast so that users can save wait time greatly. Even though products including USB interfaces meet the USB specification, they should operate under Windows or Mac OS (i.e., operating system) after bootup time. The bootup time depends upon start-up time of hardware system and how long the software comes loaded on the computer. In addition, since the USB isochronous mode packets arrive on 1 KHz intervals, the USB clock generator PLL must lock within 1 msec.
It has taken a long time to test the conventional phase-locked loops after fabrication since the test time of phase-locked loop circuits is absolutely proportional to time required the phase-locked loops to lock. In addition, it has taken a long time to test any system containing the conventional phase-locked loops. Test can occur at the wafer, at the packed-chip, multi-chip modules (i.e., MCMs), card, board, and system level. Test such as ad-hoc test, pseudo-random sequence generator (i.e., PRSG), built-in self-test (i.e., BIST) or stop-on-count-or-error (i.e., SOCE) has required clock generator PLL on chip, card, board, or system. In these tests, fast lock-in time performance highly improved system test time to keep the manufacturing cost low.
Shorter system simulation time and system test time translate into tremendous cost saving and greatly decrease time to market As stated so far, fast lock-in time performance plays a key role in modern technology and will be extremely crucial to the future technology because every system LSI has at least one PLL. However, unfortunately the conventional phase-locked loop 110 and 120 of Prior Art FIG. 1 is very inefficient to implement in an integrated circuit, system-on-chip (SOC), monolithic circuit, or discrete circuits.
Thus, what is desperately needed is a cost-effective filter-based lock-in circuit for a system which attains a drastic improvement in system startup time, system latency time, system simulation time, system test time, and time-to-market. The present invention satisfies these needs by providing filter-based lock-in circuits to speed up any system startup time, system test time, and the complete and realistic system simulation and by simply adding a filter-based lock-in circuit to a junction between a resistor and capacitor coupled serially in a filter.